From: Frank Min <[email protected]> Update firmware ID for SOC24 to support more firmware.
Signed-off-by: Frank Min <[email protected]> Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 36 ++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h index 959d60c90dcd2..2ae2c1d0f702b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h @@ -156,7 +156,41 @@ typedef enum _SOC24_FIRMWARE_ID_ { SOC24_FIRMWARE_ID_SRIOV_CSA_SDMA = 40, SOC24_FIRMWARE_ID_SRIOV_CSA_CP = 41, SOC24_FIRMWARE_ID_UMF_ZONE_PAD = 42, - SOC24_FIRMWARE_ID_MAX = 43 + SOC24_FIRMWARE_ID_SE_F32_IRAM = 43, + SOC24_FIRMWARE_ID_SE_XT_IRAM = 44, + SOC24_FIRMWARE_ID_SE_XT_DRAM = 45, + SOC24_FIRMWARE_ID_RS64_MEC_P4_STACK = 46, + SOC24_FIRMWARE_ID_RS64_MEC_P5_STACK = 47, + SOC24_FIRMWARE_ID_RS64_MEC_P6_STACK = 48, + SOC24_FIRMWARE_ID_RS64_MEC_P7_STACK = 49, + SOC24_FIRMWARE_ID_CP_F32_PFP_G0_A = 50, + SOC24_FIRMWARE_ID_CP_F32_PFP_G1_A = 51, + SOC24_FIRMWARE_ID_CP_F32_PFP_G2 = 52, + SOC24_FIRMWARE_ID_CP_F32_ME_G0_A = 53, + SOC24_FIRMWARE_ID_CP_F32_ME_G1_A = 54, + SOC24_FIRMWARE_ID_CP_F32_ME_G2 = 55, + SOC24_FIRMWARE_ID_CP_F32_CE_G0_A = 56, + SOC24_FIRMWARE_ID_CP_F32_CE_G1_A = 57, + SOC24_FIRMWARE_ID_CP_F32_CE_G2 = 58, + SOC24_FIRMWARE_ID_CP_F32_MEC2_G0 = 59, + SOC24_FIRMWARE_ID_CP_F32_MEC2_G1 = 60, + SOC24_FIRMWARE_ID_CP_F32_MEC2_G2 = 61, + SOC24_FIRMWARE_ID_GFXOFF_CSA_SDMA0 = 62, + SOC24_FIRMWARE_ID_GFXOFF_CSA_SDMA1 = 63, + SOC24_FIRMWARE_ID_GFXOFF_CSA_SDMA2 = 64, + SOC24_FIRMWARE_ID_GFXOFF_CSA_SDMA3 = 65, + SOC24_FIRMWARE_ID_RLX6_SCRATCH_SR = 66, + SOC24_FIRMWARE_ID_RLX6_SCRATCH_SR_CORE1 = 67, + SOC24_FIRMWARE_ID_CP_F32_PFP_G0_B = 68, + SOC24_FIRMWARE_ID_CP_F32_PFP_G1_B = 69, + SOC24_FIRMWARE_ID_CP_F32_ME_G0_B = 70, + SOC24_FIRMWARE_ID_CP_F32_ME_G1_B = 71, + SOC24_FIRMWARE_ID_CP_F32_CE_G0_B = 72, + SOC24_FIRMWARE_ID_CP_F32_CE_G1_B = 73, + SOC24_FIRMWARE_ID_CP_F32_MEC2_JT_G0 = 74, + SOC24_FIRMWARE_ID_CP_F32_MEC2_JT_G1 = 75, + SOC24_FIRMWARE_ID_CP_F32_MEC2_JT_G2 = 76, + SOC24_FIRMWARE_ID_MAX = 77 } SOC24_FIRMWARE_ID; typedef struct _RLC_TABLE_OF_CONTENT { -- 2.55.0
