From: Likun Gao <[email protected]> Initialize amdgpu_gfx_config using values from gc_info_v1_4.
Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 22 ++++++---- drivers/gpu/drm/amd/include/discovery.h | 42 +++++++++++++++++++ 2 files changed, 55 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 1420bb60e015e..9a04e681a0cb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2056,6 +2056,7 @@ union gc_info { struct gc_info_v1_1 v1_1; struct gc_info_v1_2 v1_2; struct gc_info_v1_3 v1_3; + struct gc_info_v1_4 v1_4; struct gc_info_v1_5 v1_5; struct gc_info_v2_0 v2; struct gc_info_v2_1 v2_1; @@ -2118,7 +2119,18 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); } - if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { + if (le16_to_cpu(gc_info->v1.header.version_minor) == 4) { + num_wgps_per_sa = le32_to_cpu(gc_info->v1_4.gc_num_rwgp0_per_sa) + + le32_to_cpu(gc_info->v1_4.gc_num_rwgp1_per_sa) + + le32_to_cpu(gc_info->v1_4.gc_num_twgp0_per_sa) + + le32_to_cpu(gc_info->v1_4.gc_num_twgp1_per_sa); + num_wgps_per_sa1 = le32_to_cpu(gc_info->v1_4.gc_num_rwgp0_per_sa1) + + le32_to_cpu(gc_info->v1_4.gc_num_rwgp1_per_sa1) + + le32_to_cpu(gc_info->v1_4.gc_num_twgp0_per_sa1) + + le32_to_cpu(gc_info->v1_4.gc_num_twgp1_per_sa1); + adev->gfx.config.max_cu_per_sh = 2 * (num_wgps_per_sa >= num_wgps_per_sa1 ? + num_wgps_per_sa : num_wgps_per_sa1); + } else if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); @@ -2128,14 +2140,6 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); } - if (le16_to_cpu(gc_info->v1.header.version_minor) == 4 || - le16_to_cpu(gc_info->v1.header.version_minor) > 5) { - dev_err(adev->dev, - "Unsupported GC info table %d.%d\n", - le16_to_cpu(gc_info->v1.header.version_major), - le16_to_cpu(gc_info->v1.header.version_minor)); - return -EINVAL; - } if (le16_to_cpu(gc_info->v1.header.version_minor) == 5) { adev->gfx.config.gc_max_num_residency_ways = le32_to_cpu(gc_info->v1_5.gc_max_num_residency_ways); adev->gfx.config.gc_cache_ways_size_in_bytes = le32_to_cpu(gc_info->v1_5.gc_cache_ways_size_in_bytes); diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h index 07199c6abc73a..f5629a4ad04a1 100644 --- a/drivers/gpu/drm/amd/include/discovery.h +++ b/drivers/gpu/drm/amd/include/discovery.h @@ -319,6 +319,48 @@ struct gc_info_v1_3 { uint32_t gc_tcc_cache_line_size; }; +struct gc_info_v1_4 { + struct gpu_info_header header; + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; + uint32_t gc_num_tcp_per_wpg; + uint32_t gc_tcp_l1_size; + uint32_t gc_num_sqc_per_wgp; + uint32_t gc_l1_instruction_cache_size_per_sqc; + uint32_t gc_l1_data_cache_size_per_sqc; + uint32_t gc_gl1c_per_sa; + uint32_t gc_gl1c_size_per_instance; + uint32_t gc_gl2c_per_gpu; + uint32_t gc_num_rwgp0_per_sa; + uint32_t gc_num_rwgp0_per_sa1; + uint32_t gc_num_rwgp1_per_sa; + uint32_t gc_num_rwgp1_per_sa1; + uint32_t gc_num_twgp0_per_sa; + uint32_t gc_num_twgp0_per_sa1; + uint32_t gc_num_twgp1_per_sa; + uint32_t gc_num_twgp1_per_sa1; +}; + struct gc_info_v1_5 { struct gpu_info_header header; uint32_t gc_num_se; -- 2.55.0
