Add two new VM ioctl operations: AMDGPU_VM_OP_SET_L2_TRAP (op = 3) AMDGPU_VM_OP_CLEAR_L2_TRAP (op = 4)
The second-level trap handler is a per-GPUVM setting. All shader waves using the GPUVM use the same handler regardless of queue type, so one SET_L2_TRAP operation configures the handler for that GPUVM. The TRAP ioctl and its associated structures are removed entirely; the ioctl number was never part of a released kernel. The TBA and TMA ranges must remain valid mappings in the GPUVM while the second-level trap handler is installed. Suggested-by: Christian König <[email protected]> Suggested-by: Alex Deucher <[email protected]> Cc: Felix Kuehling <[email protected]> Cc: Lancelot Six <[email protected]> Cc: James Zhu <[email protected]> Cc: Lijo Lazar <[email protected]> Cc: Samuel Pitoiset <[email protected]> Cc: Natalie Vock <[email protected]> Cc: Timur Kristóf <[email protected]> Cc: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 26 ++++++++ include/uapi/drm/amdgpu_drm.h | 92 ++++++++++++++++++++------ 2 files changed, 98 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 99a9605f8e15..342d0f174e8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2913,6 +2913,32 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) case AMDGPU_VM_OP_UNRESERVE_VMID: amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); break; + case AMDGPU_VM_OP_SET_L2_TRAP: + /* + * Install or replace the per-VM second-level trap handler. + * Applies to all shader waves using this GPUVM regardless of + * queue type. + */ + if (!vm->trap_obj) + return -EOPNOTSUPP; + return amdgpu_trap_vm_set_l2_trap(adev, vm, + &fpriv->userq_mgr, + vm->trap_obj, + args->in.l2trap.tba_va, + args->in.l2trap.tba_sz, + args->in.l2trap.tma_va, + args->in.l2trap.tma_sz); + case AMDGPU_VM_OP_CLEAR_L2_TRAP: + /* + * Disable the per-VM second-level trap handler. + * Evicts user queues and waits for outstanding VM work before + * clearing the handler descriptor. + */ + if (!vm->trap_obj) + return -EOPNOTSUPP; + return amdgpu_trap_vm_clear_l2_trap(adev, vm, + &fpriv->userq_mgr, + vm->trap_obj); default: return -EINVAL; } diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 42b2b09d05dd..8606d055b37e 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -644,10 +644,82 @@ struct drm_amdgpu_userq_wait { #define AMDGPU_VM_OP_RESERVE_VMID 1 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 +/** + * AMDGPU_VM_OP_SET_L2_TRAP - install or replace the second-level trap + * handler for this GPUVM. + * + * The second-level trap handler is a per-GPUVM setting. All shader waves + * using this GPUVM use the same handler regardless of queue type. + * + * TBA is the GPU virtual address of the second-level trap handler code. + * TMA is the GPU virtual address of the second-level trap handler scratch + * memory. Both ranges must be non-empty and fully mapped in this GPUVM. + * + * Before updating the handler descriptor, active user queues are evicted + * and outstanding work tracked by the GPUVM reservation is allowed to + * complete. The GPUVM root is then reserved while the TBA and TMA mappings + * are validated and the descriptor is updated. User queues are restored + * afterwards. + * + * Userspace must keep the TBA and TMA mappings valid while the second-level + * trap handler is installed. + * + * Returns: + * 0 on success; + * -EOPNOTSUPP if the first-level CWSR handler is unavailable; + * -EINVAL if TBA/TMA is invalid or not mapped in this GPUVM; + * -ETIMEDOUT if outstanding GPUVM work does not complete; + * negative errno if the GPUVM reservation or queue restore fails. + */ +#define AMDGPU_VM_OP_SET_L2_TRAP 3 + +/** + * AMDGPU_VM_OP_CLEAR_L2_TRAP - disable the second-level trap handler. + * + * Before clearing the handler descriptor, active user queues are evicted + * and outstanding work tracked by the GPUVM reservation is allowed to + * complete. The GPUVM root is then reserved while the descriptor is + * cleared. User queues are restored afterwards. + * + * The l2trap input members are ignored for this operation. + * + * After this operation succeeds, userspace may remove the second-level + * TBA and TMA mappings. + * + * Returns: + * 0 on success; + * -EOPNOTSUPP if the first-level CWSR handler is unavailable; + * -EINVAL if the GPUVM trap state is invalid; + * -ETIMEDOUT if outstanding GPUVM work does not complete; + * negative errno if the GPUVM reservation or queue restore fails. + */ +#define AMDGPU_VM_OP_CLEAR_L2_TRAP 4 + struct drm_amdgpu_vm_in { /** AMDGPU_VM_OP_* */ __u32 op; __u32 flags; + union { + struct { + /** GPU VA of second-level trap handler code buffer */ + __u64 tba_va; + /** TBA buffer size in bytes */ + __u32 tba_sz; + /** Explicit padding; tma_va starts at offset 24 */ + __u32 _pad; + /** GPU VA of second-level trap handler scratch buffer */ + __u64 tma_va; + /** TMA buffer size in bytes */ + __u32 tma_sz; + /** Padding to fix total union size at 32 bytes */ + __u32 _pad2; + } l2trap; + /** + * Padding; keeps the union at a fixed 32-byte size for + * future ops. Zero-initialise for RESERVE/UNRESERVE_VMID. + */ + __u64 _pad[4]; + }; }; struct drm_amdgpu_vm_out { @@ -1757,27 +1829,7 @@ struct drm_amdgpu_info_cwsr { __u32 min_save_area_size; }; -/* cwsr ioctl */ -#define AMDGPU_TRAP_OP_SET_L2_TRAP 1 - -struct drm_amdgpu_trap_in { - /* AMDGPU_TRAP_OP_* */ - __u32 op; - struct { - /* Level 2 trap handler base address */ - __u64 tba_va; - /* Level 2 trap handler buffer size (in bytes) */ - __u32 tba_sz; - /* Level 2 trap memory buffer address */ - __u64 tma_va; - /* Level 2 trap memory buffer size (in bytes) */ - __u32 tma_sz; - } l2trap; -}; -union drm_amdgpu_trap { - struct drm_amdgpu_trap_in in; -}; /* * Supported GPU families */ -- 2.34.1
