From: Lin Cao <[email protected]> [Why] Under SRIOV VF, GFX firmware are required to loaded.
[How] Add GFX FW list. FW contains: PFP ucode, PFP data P0-P1 ME ucode, ME data P0-P1 MEC ucode, MEC data P0-P7 MES SCH ucode and data MES KIQ ucode and data Signed-off-by: Yifan Zha <[email protected]> Signed-off-by: Lin Cao <[email protected]> Reviewed-by: Frank Min<[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 23 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 56116bcd0a3a8..ba36260b41b69 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -174,6 +174,9 @@ static int psp_init_sriov_microcode(struct psp_context *psp) case IP_VERSION(13, 0, 12): ret = psp_init_ta_microcode(psp, ucode_prefix); break; + case IP_VERSION(15, 0, 3): + adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; + break; default: return -EINVAL; } @@ -4010,6 +4013,8 @@ static int psp_load_non_psp_fw(struct psp_context *psp) IP_VERSION(11, 0, 12) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 0) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == + IP_VERSION(15, 0, 3) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 5) || amdgpu_ip_version(adev, MP0_HWIP, 0) == diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 681a9904a79e5..8b08297e4a8a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -1369,6 +1369,29 @@ bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_i return false; else return true; + case IP_VERSION(15, 0, 3): + if (ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK + || ucode_id == AMDGPU_UCODE_ID_CP_MES + || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA + || ucode_id == AMDGPU_UCODE_ID_CP_MES1 + || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA) + return false; + else + return true; default: /* lagacy black list */ if (ucode_id == AMDGPU_UCODE_ID_SDMA0 -- 2.55.0
