From: Lin Cao <[email protected]> Add ucode loading support for MEC pipe stacks P4-P7: - add GFX_FW_TYPE_RS64_MEC_P4..P7 firmware types - add AMDGPU_UCODE_ID_CP_RS64_MEC_P4..P7 ucode ids - handle P4-P7 in ucode name/init, psp fw type
Signed-off-by: Yifan Zha <[email protected]> Signed-off-by: Yiqing Yao <[email protected]> Signed-off-by: Lin Cao <[email protected]> Reviewed-by: Frank Min<[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 12 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 28 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/psp_v15_0_3.c | 12 ++++++++++ 6 files changed, 64 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 7a132e6d7e429..4e38285e90676 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1599,6 +1599,10 @@ void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: + case AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK: + case AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK: + case AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK: + case AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK: cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) adev->gfx.mec_fw->data; ucode_fw = adev->gfx.mec_fw; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 5db568fc24218..56116bcd0a3a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3726,6 +3726,18 @@ int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P4_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P5_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P6_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P7_STACK; + break; case AMDGPU_UCODE_ID_VPE_CTX: *type = GFX_FW_TYPE_VPEC_FW1; break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index e5d47f08715f3..d2ce526dd95cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -751,6 +751,14 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) return "RS64_MEC_P2_STACK"; case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: return "RS64_MEC_P3_STACK"; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK: + return "RS64_MEC_P4_STACK"; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK: + return "RS64_MEC_P5_STACK"; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK: + return "RS64_MEC_P6_STACK"; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK: + return "RS64_MEC_P7_STACK"; case AMDGPU_UCODE_ID_ISP: return "ISP"; case AMDGPU_UCODE_ID_MP5: @@ -1094,6 +1102,26 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, ucode_addr = (u8 *)ucode->fw->data + le32_to_cpu(cpv2_hdr->data_offset_bytes); break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK: + ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + ucode_addr = (u8 *)ucode->fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes); + break; case AMDGPU_UCODE_ID_VPE_CTX: ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); ucode_addr = (u8 *)ucode->fw->data + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 83e5f0627369d..35277b240f25a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -503,6 +503,10 @@ enum AMDGPU_UCODE_ID { AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, + AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK, + AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK, + AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK, + AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK, AMDGPU_UCODE_ID_CP_MEC1, AMDGPU_UCODE_ID_CP_MEC1_JT, AMDGPU_UCODE_ID_CP_MEC2, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index d54b9edcd5394..612d532494764 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -322,6 +322,10 @@ enum psp_gfx_fw_type { GFX_FW_TYPE_VPE = 102, GFX_FW_TYPE_JPEG_RAM = 128, /**< JPEG Command buffer */ GFX_FW_TYPE_P2S_TABLE = 129, + GFX_FW_TYPE_RS64_MEC_P4_STACK = 133, /* RS64 MEC stack P4 ATx */ + GFX_FW_TYPE_RS64_MEC_P5_STACK = 134, /* RS64 MEC stack P5 ATx */ + GFX_FW_TYPE_RS64_MEC_P6_STACK = 135, /* RS64 MEC stack P6 ATx */ + GFX_FW_TYPE_RS64_MEC_P7_STACK = 136, /* RS64 MEC stack P7 ATx */ GFX_FW_TYPE_MP5 = 158, /* MP5 ucode */ GFX_FW_TYPE_MAX }; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_3.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_3.c index cab3bec1e5127..33662a1aad16c 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_3.c @@ -746,6 +746,18 @@ static int psp_v15_0_3_get_fw_type(struct amdgpu_firmware_info *ucode, case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P4_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P5_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P6_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P7_STACK; + break; case AMDGPU_UCODE_ID_VPE_CTX: *type = GFX_FW_TYPE_VPEC_FW1; break; -- 2.55.0
