From: Fudongwang <[email protected]> [WHY+HOW] According to HW, change default z8 enter/exist for dcn314. SR Z8 exit = 268, change to 390. SR Z8 enter = 393, change to 601.
Signed-off-by: Fudongwang <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Dillon Varone <[email protected]> --- drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index 2f9ae79da731..1854137d5b9e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -150,8 +150,8 @@ static struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { .num_states = 5, .sr_exit_time_us = 16.5, .sr_enter_plus_exit_time_us = 18.5, - .sr_exit_z8_time_us = 268.0, - .sr_enter_plus_exit_z8_time_us = 393.0, + .sr_exit_z8_time_us = 390.0, + .sr_enter_plus_exit_z8_time_us = 601.0, .writeback_latency_us = 12.0, .dram_channel_width_bytes = 4, .round_trip_ping_latency_dcfclk_cycles = 106, -- 2.53.0
