Mesa will use it to get the slice offset in bitstream from feedback, which makes it possible to filter out SPS/PPS headers that VCE 1 and 2 FW always forces on IDR frames.
Signed-off-by: David Rosca <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 39d87f3df9e0..bfad44ec7feb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -920,6 +920,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, case 0x04000007: /* motion estimation */ case 0x04000008: /* rdo */ case 0x04000009: /* vui */ + case 0x0400000d: /* sei */ case 0x05000002: /* auxiliary buffer */ case 0x05000009: /* clock table */ break; -- 2.43.0
