From: Rafal Ostrowski <[email protected]> [WHY] Refactor DC_IP_REQUEST_CNTL to follow BLS rules: replace struct dc *dc with dce_hwseq handle in parameter structure and vtable signature, and add comprehensive hardware access guards.
[HOW] - Update struct dc_ip_request_cntl_params to store struct dce_hwseq *hws instead of struct dc *dc. - Update hwseq_private_funcs.dc_ip_request_cntl signature and dcn401 implementation to take (struct dce_hwseq *hws, bool enable). - Add null checks for hws context, registers, shifts, and masks in dcn401_dc_ip_request_cntl. - Update hwss_dc_ip_request_cntl executor and hwss_add_dc_ip_request_cntl builder. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Rafal Ostrowski <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> --- .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 12 +++++++----- .../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 6 +++--- .../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 +- drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 2 +- .../drm/amd/display/dc/hwss/hw_sequencer_private.h | 2 +- 5 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index da98afee558f..7b93f57aff85 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -4051,12 +4051,10 @@ void hwss_dpp_root_clock_control(union block_sequence_params *params) void hwss_dc_ip_request_cntl(union block_sequence_params *params) { - struct dc *dc = params->dc_ip_request_cntl_params.dc; + struct dce_hwseq *hws = params->dc_ip_request_cntl_params.hws; bool enable = params->dc_ip_request_cntl_params.enable; - struct dce_hwseq *hws = dc->hwseq; - if (hws->funcs.dc_ip_request_cntl) - hws->funcs.dc_ip_request_cntl(dc, enable); + hws->funcs.dc_ip_request_cntl(hws, enable); } void hwss_dccg_update_dpp_dto(union block_sequence_params *params) @@ -4964,9 +4962,13 @@ void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, struct dc *dc, bool enable) { + if (!seq_state || !seq_state->steps || !seq_state->num_steps || !dc || + !dc->hwseq || !dc->hwseq->funcs.dc_ip_request_cntl) + return; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { seq_state->steps[*seq_state->num_steps].func = DC_IP_REQUEST_CNTL; - seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.hws = dc->hwseq; seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.enable = enable; (*seq_state->num_steps)++; } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 0abdfc55290c..efff09784f45 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -3598,10 +3598,10 @@ void dcn401_post_unlock_reset_opp_sequence( } } -void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable) +void dcn401_dc_ip_request_cntl(struct dce_hwseq *hws, bool enable) { - struct dce_hwseq *hws = dc->hwseq; - + if (!hws || !hws->ctx || !hws->regs || !hws->shifts || !hws->masks) + return; if (REG(DC_IP_REQUEST_CNTL)) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, enable ? 1 : 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index ecaeb192bca3..9df72e980e7a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -185,7 +185,7 @@ void dcn401_post_unlock_reset_opp_sequence( struct pipe_ctx *opp_head, struct block_sequence_state *seq_state); -void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable); +void dcn401_dc_ip_request_cntl(struct dce_hwseq *hws, bool enable); void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 7800b0501c39..bd005aaf9317 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -711,7 +711,7 @@ struct dpp_root_clock_control_params { }; struct dc_ip_request_cntl_params { - struct dc *dc; + struct dce_hwseq *hws; bool enable; }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h index 9586029dcec1..b2e63363066f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h @@ -225,7 +225,7 @@ struct hwseq_private_funcs { struct hubp *primary_hubp); void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only); void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*dc_ip_request_cntl)(struct dc *dc, bool enable); + void (*dc_ip_request_cntl)(struct dce_hwseq *hws, bool enable); void (*program_cm_hist)(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); -- 2.43.0
