Hi all, This series adds the CWSR infrastructure required for user queues and extends the trap handling support to provide a userspace second-level trap handler.
The first part of the series adds the CWSR infrastructure, integrates it with user queues, and exposes the required CWSR userspace interfaces. The trap handling infrastructure is then extended to support a second-level userspace trap handler. The first-level TMA contains the second-level TBA and TMA addresses and provides helpers to install, clear, and update the second-level trap state. The first-level trap state is owned by the GPUVM so user queues and kernel-managed queues using the same GPUVM share the same trap state. For kernel-managed VMIDs, the first-level TBA and TMA registers are programmed through the GFXHUB setup path. The implementation handles the generation-specific trap enablement and multi-XCC programming requirements. The second-level trap handler is controlled through new SET_L2_TRAP and CLEAR_L2_TRAP operations on the existing VM ioctl. There is no separate TRAP ioctl. The series also includes the locking and lifetime fixes required by the CWSR/trap infrastructure. In particular, the per-VM TMA BO uses the VM root reservation to avoid recursive ww_mutex acquisition, and VM mapping validation is performed while holding the VM root BO reservation. The patches are organized as follows: 1. Add the core CWSR infrastructure for user queues. 2. Integrate CWSR with the user queue path. 3. Add the CWSR userspace interfaces. 4. Add the second-level trap handler infrastructure. 5. Move first-level trap state ownership to the GPUVM. 6. Program first-level trap TBA/TMA for kernel-managed VMIDs. 7. Add SET_L2_TRAP and CLEAR_L2_TRAP operations to the VM ioctl. The series has been rebased onto amd-staging-drm-next and build tested. Thanks, Srini Lijo Lazar (4): drm/amdgpu: Add CWSR infrastructure for user queues drm/amdgpu: Integrate CWSR with user queues drm/amdgpu: Add CWSR userspace interfaces drm/amdgpu: Add second-level trap handler infrastructure Srinivasan Shanmugam (3): drm/amdgpu: Make first-level trap state GPUVM-owned drm/amdgpu: Program trap TBA/TMA for kernel-managed VMIDs drm/amdgpu/uapi: Add SET/CLEAR L2 TRAP to VM ioctl drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 24 + drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c | 723 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h | 148 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 24 + drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 60 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 17 +- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 22 + drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 14 + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 29 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 16 + drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c | 38 + drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c | 38 + drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c | 53 ++ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 41 ++ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 53 ++ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 38 + drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 42 ++ drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 46 ++ drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 46 ++ drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 106 ++- include/uapi/drm/amdgpu_drm.h | 91 +++ 27 files changed, 1676 insertions(+), 41 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h -- 2.34.1
