On 10/8/26 09:05, Srinivasan Shanmugam wrote: > From: Lijo Lazar <[email protected]> > > Add an ioctl to return the size information required for CWSR regions. > > Add CWSR parameters to the user queue ioctl so userspace can provide > the GPU virtual address and allocated size of the save/restore buffer. > The parameters are supported for user compute queues. > > Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Christian König <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 21 +++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 13 +++++++---- > include/uapi/drm/amdgpu_drm.h | 27 ++++++++++++++++++++++ > 3 files changed, 57 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > index f3945b3988d8..147c0bd02731 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > @@ -1429,6 +1429,27 @@ int amdgpu_info_ioctl(struct drm_device *dev, void > *data, struct drm_file *filp) > return -EINVAL; > } > } > + case AMDGPU_INFO_CWSR: { > + struct drm_amdgpu_info_cwsr cwsr_info; > + int num_xcc, r; > + > + fpriv = (struct amdgpu_fpriv *)filp->driver_priv; > + if (!amdgpu_cwsr_is_enabled(adev) || !fpriv->cwsr_trap) > + return -EOPNOTSUPP; > + num_xcc = amdgpu_xcp_get_num_xcc(adev->xcp_mgr, fpriv->xcp_id); > + cwsr_info.ctl_stack_size = > + adev->cwsr_info->xcc_ctl_stack_sz * num_xcc; > + cwsr_info.dbg_mem_size = > + adev->cwsr_info->xcc_dbg_mem_sz * num_xcc; > + cwsr_info.min_save_area_size = > + amdgpu_cwsr_size_needed(adev, num_xcc); > + r = copy_to_user(out, &cwsr_info, > + min((size_t)size, sizeof(cwsr_info))) ? > + -EFAULT : > + 0; > + return r; > + } > + > default: > DRM_DEBUG_KMS("Invalid request %d\n", info->query); > return -EINVAL; > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c > b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c > index 3b7a1479fbf7..5311e1ad0201 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c > @@ -461,11 +461,9 @@ static int mes_userq_mqd_create(struct > amdgpu_usermode_queue *queue, > num_xcc = amdgpu_xcp_get_num_xcc(adev->xcp_mgr, > fpriv->xcp_id); > cwsr_params.ctx_save_area_address = > - userq_props->ctx_save_area_addr; > + compute_mqd->ctx_save_area_va; > cwsr_params.cwsr_sz = > - userq_props->ctx_save_area_size; > - userq_props->ctl_stack_size = > - adev->cwsr_info->xcc_ctl_stack_sz * num_xcc; > + compute_mqd->ctx_save_area_size; > > r = amdgpu_bo_reserve(queue->vm->root.bo, false); > if (r) { > @@ -480,6 +478,13 @@ static int mes_userq_mqd_create(struct > amdgpu_usermode_queue *queue, > kfree(compute_mqd); > goto free_mqd; > } > + > + userq_props->ctx_save_area_addr = > + compute_mqd->ctx_save_area_va; > + userq_props->ctx_save_area_size = > + compute_mqd->ctx_save_area_size; > + userq_props->ctl_stack_size = > + adev->cwsr_info->xcc_ctl_stack_sz * num_xcc; > } > > kfree(compute_mqd); > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > index 29009f6aabde..9317018330ec 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -470,6 +470,17 @@ struct drm_amdgpu_userq_mqd_compute_gfx11 { > * to get the size. > */ > __u64 eop_va; > + /** > + * @ctx_save_area_va: Virtual address of the GPU memory for > save/restore buffer. > + * This must be from a separate GPU object, and use AMDGPU_INFO IOCTL > + * to get the size. This includes control stack, wave context and > debugger memory. > + */ > + __u64 ctx_save_area_va; > + /** > + * @ctx_save_area_size: Total size (in bytes) allocated for > save/restore buffer. > + * Use AMDGPU_INFO IOCTL to get the size. > + */ > + __u32 ctx_save_area_size; > }; > > /* userq signal/wait ioctl */ > @@ -1289,6 +1300,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { > #define AMDGPU_INFO_GPUVM_FAULT 0x23 > /* query FW object size and alignment */ > #define AMDGPU_INFO_UQ_FW_AREAS 0x24 > +/* query CWSR size and alignment */ > +#define AMDGPU_INFO_CWSR 0x25 > > #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 > #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff > @@ -1668,6 +1681,20 @@ struct drm_amdgpu_info_uq_metadata { > }; > }; > > +/** > + * struct drm_amdgpu_info_cwsr - cwsr information > + * > + * Gives cwsr related size details. User needs to allocate buffer based on > this. > + */ > +struct drm_amdgpu_info_cwsr { > + /* Control stack size */ > + __u32 ctl_stack_size; > + /* Debug memory area size */ > + __u32 dbg_mem_size; > + /* Minimum save area size required */ > + __u32 min_save_area_size; > +}; > + > /* > * Supported GPU families > */
