From: Leon Huang <[email protected]> [Why] AS-SDP V3 extends the coasting vtotal field from 16 bits to 24 bits by adding DB9 for bits[23:16] for VESA Panel Replay.
[How] Parse the capability from DPCD and apply when VESA PR is enabled Reviewed-by: Robin Chen <[email protected]> Signed-off-by: Leon Huang <[email protected]> Signed-off-by: Ray Wu <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 +- .../amd/display/modules/inc/mod_info_packet.h | 5 +++ .../display/modules/info_packet/info_packet.c | 34 +++++++++++++++++-- 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index b0e91b321f43..9353292edc0b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -922,7 +922,8 @@ union dpcd_dprx_feature_enumeration_list_cont_1 { uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1; uint8_t RESERVED0: 2; uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1; - uint8_t RESERVED1: 3; + uint8_t AS_SDP_VERSION_3_SUPPORTED: 1; + uint8_t RESERVED1: 2; } bits; uint8_t raw; }; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h index 5181d889fe7f..45ba1a974094 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h @@ -52,9 +52,11 @@ enum adaptive_sync_sdp_version { AS_SDP_VER_0 = 0x0, AS_SDP_VER_1 = 0x1, AS_SDP_VER_2 = 0x2, + AS_SDP_VER_3 = 0x3, }; #define AS_DP_SDP_LENGTH (9) +#define AS_DP_SDP_V3_LENGTH (0xA) struct frame_duration_op { bool support; @@ -78,6 +80,9 @@ void mod_build_adaptive_sync_infopacket(const struct dc_stream_state *stream, void mod_build_adaptive_sync_infopacket_v2(const struct dc_stream_state *stream, const struct AS_Df_params *param, struct dc_info_packet *info_packet); +void mod_build_adaptive_sync_infopacket_v3(const struct dc_stream_state *stream, + const struct AS_Df_params *param, struct dc_info_packet *info_packet); + void mod_build_adaptive_sync_infopacket_v1(struct dc_info_packet *info_packet); #endif diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c index 32b697f46788..48d0e164e62b 100644 --- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c @@ -770,9 +770,12 @@ void mod_build_adaptive_sync_infopacket(const struct dc_stream_state *stream, case FREESYNC_TYPE_PCON_IN_WHITELIST: case ADAPTIVE_SYNC_TYPE_EDP: if (stream && stream->link->replay_settings.config.replay_supported && - stream->link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) - mod_build_adaptive_sync_infopacket_v2(stream, param, info_packet); - else + stream->link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) { + if (stream->link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.bits.AS_SDP_VERSION_3_SUPPORTED) + mod_build_adaptive_sync_infopacket_v3(stream, param, info_packet); + else + mod_build_adaptive_sync_infopacket_v2(stream, param, info_packet); + } else mod_build_adaptive_sync_infopacket_v1(info_packet); break; case ADAPTIVE_SYNC_TYPE_NONE: @@ -815,3 +818,28 @@ void mod_build_adaptive_sync_infopacket_v2(const struct dc_stream_state *stream, } } +void mod_build_adaptive_sync_infopacket_v3(const struct dc_stream_state *stream, + const struct AS_Df_params *param, + struct dc_info_packet *info_packet) +{ + info_packet->valid = true; + // HEADER {HB0, HB1, HB2, HB3} = {00, Type, Version, Length} + // For eDP VESA Panel Replay the coasting vtotal (DB7-DB9) is filled by the + // DMUB firmware,so only the header is built. + info_packet->hb0 = 0x00; + info_packet->hb1 = 0x22; + info_packet->hb2 = AS_SDP_VER_3; + info_packet->hb3 = AS_DP_SDP_V3_LENGTH; + + if (param) { + //Payload + info_packet->sb[0] = param->supportMode; //1: AVT; 0: FAVT + info_packet->sb[1] = (stream->timing.v_total & 0x00FF); + info_packet->sb[2] = (stream->timing.v_total & 0xFF00) >> 8; + //info_packet->sb[3] = 0x00; Target RR, not use fot AVT + info_packet->sb[4] = (param->increase.support << 6 | param->decrease.support << 7); + info_packet->sb[5] = param->increase.frame_duration_hex; + info_packet->sb[6] = param->decrease.frame_duration_hex; + } +} + -- 2.43.0
