From: Piotr Maziarz <[email protected]> [Why] dp_trace_source_sequence() only writes DPCD when dc->debug.enable_driver_sequence_debug is set, and it reads that flag at execute time. The step was therefore emitted on every DP flip and then discarded by the callee whenever the flag was clear. The flag is set once at init, so the decision belongs in the build phase.
The fast-sequence site also hand-wrote the step, bypassing the bounds check in hwss_add_dp_trace_source_sequence(), and the golden dumper had no case for the operation despite core_golden.hpp carrying .source. [How] Emit the step only when the signal is DP and the flag is set. The guard inside dp_trace_source_sequence() stays, as many non-BLS callers rely on it. Use the bounds-checked helper in hwss_build_fast_sequence(), add the dumper case, and set the flag in FAST_UPDATE_INFO_FRAME so its golden still matches. No functional change when the flag is set. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Piotr Maziarz <[email protected]> Signed-off-by: Ray Wu <[email protected]> --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++- drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 10 ++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 05e8fcc710e3..8cf6edbd39c9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4216,7 +4216,9 @@ static void commit_planes_do_stream_update_sequence(struct dc *dc, resource_build_info_frame(pipe_ctx); add_update_info_frame_sequence(&seq_state, pipe_ctx); - if (dc_is_dp_signal(pipe_ctx->stream->signal)) + /* The step only writes DPCD when the debug flag is set, so gate emission on it here. */ + if (dc_is_dp_signal(pipe_ctx->stream->signal) && + dc->debug.enable_driver_sequence_debug) hwss_add_dp_trace_source_sequence(&seq_state, pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index d6177463c0a0..86957b4d182a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1292,12 +1292,10 @@ void hwss_build_fast_sequence(struct dc *dc, block_sequence[*num_steps].func = HWSS_UPDATE_INFO_FRAME; (*num_steps)++; - if (dc_is_dp_signal(pipe_ctx->stream->signal)) { - block_sequence[*num_steps].params.dp_trace_source_sequence_params.link = pipe_ctx->stream->link; - block_sequence[*num_steps].params.dp_trace_source_sequence_params.source = DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME; - block_sequence[*num_steps].func = DP_TRACE_SOURCE_SEQUENCE; - (*num_steps)++; - } + /* The step only writes DPCD when the debug flag is set, so gate emission on it here. */ + if (dc_is_dp_signal(pipe_ctx->stream->signal) && dc->debug.enable_driver_sequence_debug) + hwss_add_dp_trace_source_sequence(&seq_state, pipe_ctx->stream->link, + DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); } if (dc->hwss.set_dmdata_attributes && stream->update_flags.bits.dmdata && -- 2.43.0
