Update SET_SHADER_DEBUGGER packet with tcp_watch_addr_lo/hi fields. Remove direct TCP_WATCH register writes from set_address_watch().
v2: Add missing code for mes_v12_1.c Assisted-by: claude-code:claude-sonnet-4 Signed-off-by: David Belanger <[email protected]> Reviewed-by: Michael Chen <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c | 12 ------------ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c | 12 ------------ drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 6 ++++++ drivers/gpu/drm/amd/include/mes_v12_api_def.h | 3 +++ 5 files changed, 15 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c index 62b9db64368e3..004d0253f60db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c @@ -322,13 +322,9 @@ static uint32_t kgd_gfx_v12_set_address_watch(struct amdgpu_device *adev, uint32_t debug_vmid, uint32_t inst) { - uint32_t watch_address_high; - uint32_t watch_address_low; uint32_t watch_address_cntl; watch_address_cntl = 0; - watch_address_low = lower_32_bits(watch_address); - watch_address_high = upper_32_bits(watch_address) & 0xffff; watch_address_cntl = REG_SET_FIELD(watch_address_cntl, TCP_WATCH0_CNTL, @@ -345,14 +341,6 @@ static uint32_t kgd_gfx_v12_set_address_watch(struct amdgpu_device *adev, VALID, 1); - WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + - (watch_id * TCP_WATCH_STRIDE)), - watch_address_high); - - WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + - (watch_id * TCP_WATCH_STRIDE)), - watch_address_low); - return watch_address_cntl; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c index bda9578c40359..ca82eac6035ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c @@ -325,13 +325,9 @@ static uint32_t kgd_gfx_v12_1_set_address_watch(struct amdgpu_device *adev, uint32_t debug_vmid, uint32_t inst) { - uint32_t watch_address_high; - uint32_t watch_address_low; uint32_t watch_address_cntl; watch_address_cntl = 0; - watch_address_low = lower_32_bits(watch_address); - watch_address_high = upper_32_bits(watch_address) & 0x1ffffff; watch_address_cntl = REG_SET_FIELD(watch_address_cntl, TCP_WATCH0_CNTL, @@ -348,14 +344,6 @@ static uint32_t kgd_gfx_v12_1_set_address_watch(struct amdgpu_device *adev, VALID, 1); - WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) + - (watch_id * TCP_WATCH_STRIDE)), - watch_address_high, inst); - - WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) + - (watch_id * TCP_WATCH_STRIDE)), - watch_address_low, inst); - return watch_address_cntl; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 0f8b9e59d394e..fdb21739c1d53 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -981,6 +981,12 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, input->set_shader_debugger.tcp_watch_cntl, sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); + for (int i = 0; i < 4; i++) { + misc_pkt.set_shader_debugger.tcp_watch_addr_lo[i] = + lower_32_bits(input->set_shader_debugger.watch_addresses[i]); + misc_pkt.set_shader_debugger.tcp_watch_addr_hi[i] = + upper_32_bits(input->set_shader_debugger.watch_addresses[i]) & 0xffff; + } misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; break; case MES_MISC_OP_CHANGE_CONFIG: diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index ef81c5a23b9da..3c154529aff30 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -622,6 +622,12 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes, memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, input->set_shader_debugger.tcp_watch_cntl, sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); + for (int i = 0; i < 4; i++) { + misc_pkt.set_shader_debugger.tcp_watch_addr_lo[i] = + lower_32_bits(input->set_shader_debugger.watch_addresses[i]); + misc_pkt.set_shader_debugger.tcp_watch_addr_hi[i] = + upper_32_bits(input->set_shader_debugger.watch_addresses[i]) & 0xffff; + } misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; break; case MES_MISC_OP_CHANGE_CONFIG: diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h index 3e214cb4f6e13..090c9142674e3 100644 --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h @@ -805,6 +805,9 @@ struct SET_SHADER_DEBUGGER { uint32_t spi_gdbg_per_vmid_cntl; uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL uint32_t trap_en; + uint32_t tcp_watch_addr_lo[4]; // TCP_WATCHx_ADDR_L + uint32_t tcp_watch_addr_hi[4]; // TCP_WATCHx_ADDR_H + uint32_t process_context_array_index; }; struct SET_GANG_SUBMIT { -- 2.55.0
