Hi David,

well I just figured that this is a misunderstanding.

Accessing this register and some other deprecated registers can cause problem when invalidating VMHUBs.

This register itself isn't deprecated, the wording in a patch fixing things is just a bit unclear.

Question is is that register still accessed regularly or is it value cached after startup?

Regards,
Christian.

Am 07.03.2018 um 15:25 schrieb Mao, David:
We requires base driver to provide the mask of disabled RB.
This is why kernel read the CC_RB_BACKEND_DISABLE to collect the harvest configuration.
Where did you get to know that the register is deprecated?
I think it should still be there.

Best Regards,
David

On Mar 7, 2018, at 9:49 PM, Liu, Monk <monk....@amd.com <mailto:monk....@amd.com>> wrote:

+ UMD guys
Hi David
Do you know if*GC_USER_RB_BACKEND_DISABLE is still exist for gfx9/vega10 ?*
**
*We found*CC_RB_BACKEND_DISABLE was deprecated but looks it is still in use in kmd, so
I want to check with you both of above registers
Thanks
/Monk
*From:*amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org]*On Behalf Of*Christian K?nig
*Sent:*2018年3月7日20:26
*To:*Liu, Monk <monk....@amd.com <mailto:monk....@amd.com>>; Deucher, Alexander <alexander.deuc...@amd.com <mailto:alexander.deuc...@amd.com>>
*Cc:*amd-gfx@lists.freedesktop.org <mailto:amd-gfx@lists.freedesktop.org>
*Subject:*Re: deprecated register issues
Hi Monk,

I honestly don't have the slightest idea why we are still accessing CC_RB_BACKEND_DISABLE. Maybe it still contains some useful values?

Key point was that we needed to stop accessing it all the time to avoid triggering problems.

Regards,
Christian.

Am 07.03.2018 um 13:11 schrieb Liu, Monk:

    Hi Christian

    I remember you and AlexD mentioned that a handful registers are
    deprecated for greenland (gfx9)

    e.g. CC_RB_BACKEND_DISABLE

    do you know why we still have this routine ?

    staticu32
    gfx_v9_0_get_rb_active_bitmap(structamdgpu_device *adev)
    {
        u32 data, mask;
        data =RREG32_SOC15(GC,
    0, mmCC_RB_BACKEND_DISABLE);
        data |=RREG32_SOC15(GC,
    0, mmGC_USER_RB_BACKEND_DISABLE);
        data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
        data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
        mask
    =amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
    adev->gfx.config.max_sh_per_se);
    return(~data) & mask;
    }

    see that it still read CC_RB_BACKEND_DISABLE

    thanks

    /Monk



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