Change-Id: I2b45d765f1f60252fa1c02aced94f8100d575ddc
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Feifei Xu <[email protected]>
Acked-by: John Bridgman <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++++++--
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 9 +++++++--
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index acfbd2d..0d72f52 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -155,8 +155,13 @@ static void gfxhub_v1_0_init_cache_regs(struct
amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
tmp = mmVM_L2_CNTL4_DEFAULT;
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+ if (adev->gmc.zfb_size > 0) {
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
+ } else {
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+ }
WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 3dd5816..bd3777a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -166,8 +166,13 @@ static void mmhub_v1_0_init_cache_regs(struct
amdgpu_device *adev)
}
tmp = mmVM_L2_CNTL4_DEFAULT;
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+ if (adev->gmc.zfb_size > 0) {
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
+ } else {
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+ }
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
}
--
2.7.4
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