Am Mittwoch, den 11.04.2018, 20:26 +0200 schrieb Christian König: > Am 11.04.2018 um 19:11 schrieb Robin Murphy: > > For dma_map_sg(), DMA API implementations are free to merge consecutive > > segments into a single DMA mapping if conditions are suitable, thus the > > resulting DMA addresses may be packed into fewer entries than > > ttm->sg->nents implies. > > > > drm_prime_sg_to_page_addr_arrays() does not account for this, meaning > > its callers either have to reject the 0 < count < nents case or risk > > getting bogus addresses back later. Fortunately this is relatively easy > > to deal with having to rejig structures to also store the mapped count, > > since the total DMA length should still be equal to the total buffer > > length. All we need is a separate scatterlist cursor to iterate the DMA > > addresses separately from the CPU addresses. > > Mhm, I think I like Sinas approach better. > > See the hardware actually needs the dma_address on a page by page basis. > > Joining multiple consecutive pages into one entry is just additional > overhead which we don't need.
But setting MAX_SEGMENT_SIZE will probably prevent an IOMMU that might be in front of your GPU to map large pages as such, causing additional overhead by means of additional TLB misses and page walks on the IOMMU side. And wouldn't you like to use huge pages at the GPU side, if the IOMMU already provides you the service of producing one large consecutive address range, rather than mapping them via a number of small pages? Detecting such a condition is much easier if the DMA map implementation gives you the coalesced scatter entries. Regards, Lucas _______________________________________________ amd-gfx mailing list firstname.lastname@example.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx