On Thu, Dec 28, 2017 at 10:33 PM, zap <calmst...@posteo.de> wrote: > Are the shakti processors arm based
HELL no!!! why do you think they tried to bribe him to shut the project down!! oops did i mention that on a public mailing list? mwahahaa > for the architecture or some new > architecture or a different one. RISC-V. they are however doing it as a complete reimplementation, using a design system that's based on.... Haskell :) it's like myhdl.org (which is python) except it's Haskell -> Verilog. the advantage of that is that it's REALLY quick to write stuff in... and it has the advantage of being *formally mathematically provable*. unlike Chisel, which is what the rocket-chip is based on. also they're going for an 8 stage pipeline not 5, so the max speed is around 2.5ghz where rocket-chip gets around 1.5ghz in 40nm, http://bitbucket.org/casl > I believe you said the M class is supposed to be less than 1W. Which > sounds absolutely insane. Dunno how they will do that, but it looks > interesting especially considering the blazing speed it says on the charts. 120mW per core it's easily achievable. i mentioned that the EOMA68 power budget is 2.5 watts and madhu laughed: do the math, you can get 16 SMP cores into 2.5 watts :) l. _______________________________________________ arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netb...@files.phcomp.co.uk
