On Jan 5, 2018, at 21:50, Luke Kenneth Casson Leighton <[email protected]> wrote: >> On Fri, Jan 5, 2018 at 4:02 PM, Richard Wilbur <[email protected]> >> wrote: >> On Fri, Jan 5, 2018 at 4:05 AM, Luke Kenneth Casson Leighton >> <[email protected]> wrote: >>> On Fri, Jan 5, 2018 at 8:27 AM, Richard Wilbur <[email protected]> >>> wrote: >>>> On Fri, Jan 5, 2018 at 1:00 AM, Luke Kenneth Casson Leighton >>>> <[email protected]> wrote: > > it's not. basically the trick has been, due to cramped space, to put > at least 2 VIAs around power decoupling capacitors (not done by me), > and they're just on the edge. space is pretty crowded and all > previous boards worked fine (and there's been a *lot* of > pre-production boards now).
In that case, no problem. >> But I would definitely check out C3 on layer 1 as there seems to be a >> via in the middle of one of the pads. (Marked with red arrow in >> attached picture.) > > yehyeh good call that one was me, i had to reorganise the nearby > (East) power capacitors, and shuffle (West) the components next door, > in order to fit two (horizontal) 0603 4.7uF where there was previously > one (vertical) 0805 10uF. > > shuffled that VIA up as there's plenty of space. > > iiii think we're good. Well I'm glad I looked and you had chance to fix it! > now the only concern is, blasted frickin apple, has sucked world-wide > demand not just for the entire supply of 0.1 10 and 100uF capacitors > but f*****g DDR3 and eMMC *as well*. > > i now have to be extremely careful on selecting the right DDR3 RAM > ICs... *sigh*. So the situation is the chips at the speed you designed for are much more expensive while faster ones are cheaper? So the trick is how to choose a faster chip and integrate successfully into a system running at lower speed than it is specified for? _______________________________________________ arm-netbook mailing list [email protected] http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to [email protected]
