Hello, We are announcing the first release and public availability of the ARTIQ "Phaser" project!
This ARTIQ branch contains a proof-of-concept design of a GHz-datarate multichannel direct digital synthesizer (DDS) compatible with ARTIQ's RTIO channels. In later developments this proof-of-concept can be expanded to provide a two-tone output with spline modulation and multi-DAC synchronization. Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Generator project. See https://github.com/m-labs/sayma and https://github.com/m-labs/artiq-hardware. The hardware required to use the ARTIQ phaser branch is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-noise (2 GHz in the default configuration) reference clock. Some of the features are: * 4 channels * 500 MHz data rate per channel (KC705 limitation) * 4x interpolation to 2 GHz DAC sample rate * 10 GHz JESD204B lane rate * Real-time control over amplitude, frequency, phase of each channel through ARTIQ RTIO commands * Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel support * SPI registers and register bits exposed as human readable names * Parametrized JESD204B core (also capable of operation with eight lanes) * The code can be reconfigured. Possible alternative configurations are: support 2 channels at 1 GHz datarate, support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz). Attached is an oscilloscope screenshot showing the output of a demo experiment that exercises multiple ways of setting phases, frequencies and amplitues in a fully deterministic and RTIO synchronized fashion. The code of the demo is at: https://github.com/m-labs/artiq/blob/4b4fd32e3d756e555c593ba33a621c6602b32e5c/artiq/examples/phaser/repository/demo.py We are still putting on a few finishing touches. Currently one issue is that JESD links do not always come up successfully at the highest lane rate of 10 GHz while it comes up reliably at 5 GHz. Compilation, installation and usage instructions are at: https://github.com/m-labs/artiq/blob/phaser/README_PHASER.rst Feel free to submit issues, questions, and problems. The code that was developed for this project is located in several repositories: In ARTIQ, the SAWG and Phaser code: https://github.com/m-labs/artiq/compare/phaser The CORDIC core has been reused from the PDQ2 gateware https://github.com/m-labs/pdq2 The Migen/MiSoC JESD204B core: https://github.com/m-labs/jesd204b (There may be some reshuffling of code in the future). This work was supported by the Army Research Lab. Please also feel free to forward this to other interested parties. Regards, -- Robert Jördens.
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