On Fri, Jul 13, 2018 at 6:06 PM Slichter, Daniel H. (Fed) via ARTIQ <[email protected]> wrote: > I think we will really need the 8x interleaving at the RTIO clock rate, > because 1 GSPS is pretty critical (600 MSPS is marginal or a non-starter for > most of our use cases). This to me seems much more important than > maintaining some kind of more arbitrary flexibility for DUC. I am a little > unclear on others' use cases regarding DUC on the FPGA itself, but it seems > to me that simply being able to shift the output by integer multiples of fs/8 > (or fs/16, perhaps) should be more than satisfactory. It would appear to me > that any tuning with finer frequency resolution can/should be done with the > baseband signals coming out of the 8 interleaved generation blocks. > Sebastien, are you saying that even this level of DUC presents substantial > challenge?
No. That was exactly my proposal. On top of that there are probably more possibilities to simplify this dramatically. You just need to get away from specifying sample rates and details of the DSP chain and start specifying the actual use cases. Robert. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
