Thanks for the responses I will use the one instead of two.
-----Original Message-----
From: IBM Mainframe Assembler List
[mailto:[email protected]] On Behalf Of Bill Fairchild
Sent: Wednesday, August 18, 2010 4:19 PM
To: [email protected]
Subject: Re: CDS and alignment question
You can (arguably) "improve" the two Load Address instructions by
replacing them with this one instructions:
LAY R12,4096(,R11)
LAY is a 64-bit addressing instruction that is like LA except that you
can have a 20-bit displacement instead of only a 12-bit displacement.
This also assumes your code will run only on newer machines that have
64-bit addressing, newer meaning not more than about 10 years old.
Bill Fairchild
Rocket Software
-----Original Message-----
From: IBM Mainframe Assembler List
[mailto:[email protected]] On Behalf Of Ward, Mike S
Sent: Wednesday, August 18, 2010 3:51 PM
To: [email protected]
Subject: Re: CDS and alignment question
I have always used something like this:
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LR R11,R15
USING QMGREX01,R11,R12
LA R12,4095(R11)
LA R12,1(R12) <----------------- noticed that I added 1 to
the 4095 bump.
LR R8,R1
USING WORKAREA,R13
Is this not the way to do it?
-----Original Message-----
From: IBM Mainframe Assembler List
[mailto:[email protected]] On Behalf Of glen
herrmannsfeldt
Sent: Tuesday, August 17, 2010 1:56 PM
To: [email protected]
Subject: Re: CDS and alignment question
It is the address in memory that matters.
This reminds me of programs with two base registers, using LA
to set the registers such that the offset of the second is 4095
from the first. All instruction addresses (an branch instructions)
will then have an odd offset, legal but it looks funny.
On the other hand, consider all the wasted bits in even offset
branch instructions.
-- glen
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