Likely my post isn't helpful (but it's been awhile since I've cluttered up the
Assembler list and here's my chance).
I use TAM to figure out what mode mypgm has been called in and can act on it
later:
mypgm AMODE ANY CAN BE INVOKED BY 31 OR 24-BIT CALLER
USING *,R15 BASE REGISTERS
AHI R2,0 * EYECATCHER INSTRUCTION FOR TRACE *
ST R15,LOADADDR ADDRESS WHERE CALLABLE ROUTINE LOADED
STM R0,R15,SAVEREGS SAVE REGISTERS INTO THIS ROUTINE
USING NUCON,R0 CMS NUCLEUS ADDRESSABILITY
USING DATATBL2,R7 DATA TABLE2 ADDRESSING
USING WORK1,R8 ONLINE WORK AREA ADDRESSABILITY
USING DATAPNTR,R10 DATA POINTER ADDRESSING
LR R2,R1 COPY COBOL PARM AREA ADDRESS
L R1,AUSER ADDRESS OF CMS USER SAVE AREA
L R8,0(R1) ADDRESS OF ONLINE WORK AREA
MVC W1CBLPS1,0(R2) SAVE ADDR. FIRST PASS PARM GRP
TAM CALLED IN 24-BIT MODE?
<--------------- TAM
BNZ *+8 NO-ADDR PASSED SHOULD ALREADY BE OK
NI W1CBLPS1,X'00' CLEAR HIGH ORDER BYTE OF PARM1 ADDR
Thanks,
- Mike Hartman
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu] On
Behalf Of McKown, John
Sent: Thursday, September 16, 2010 1:12 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: BSM question on z
I think BSM was first introduced with the 31 bit addressing, whatever machine
that was. I don't care and it's not relevant. I don't know why I even said that.
Anyway, on a z machine, BSM is a way to branch while setting the AMODE from
<whatever> to 24, 31, or 64. Basic logic would be something like:
In the follow IC means the Instruction Counter portion of the PSW.
if branch-to address in second operand is odd then do
set amode in PSW to 64 bit
copy bits 0..62 of second operand to IC bits 0..62
set bit 63 of IC to 0
end
else if bit 32 in second operand is '1'b then do
set amode in PSW to 31 bit
copy bits 33..63 of the second operand to IC bits 33..63
set bits 0..32 of IC to zero.
end
else
set amode in PSW to 24 bit
copy bits 39..63 of second operand to IC bits 39..63
set bits 0..38 of IC to zero
end
I'm ignoring what happens to the first operand, but basically either bit 63 is
set if AMODE(64), else bit 32 is set if AMODE(31), else bit 32 is zeroed if
AMODE(24).
Now, given the above. Why does HLASM think that both operands to the BSM
instruction should be 32 bit registers? My output testing looks like:
000003D4 0B0E 665 BSM R0_64,R14_64
** ASMA323W Symbol R0_64 has incompatible type with general register field
** ASMA323W Symbol R14_64 has incompatible type with general register field
** ASMA435I Record 166 in TSH009.SOURCE.ASM(SHOWREGS) on volume: SGLB14
000003D6 0B0E 666 BSM R0_32,R14_32
000003D8 0B0E 667 BSM R0,R14
** ASMA324I Symbol R0 may have incompatible type with general register field
** ASMA324I Symbol R14 may have incompatible type with general register field
** ASMA435I Record 168 in TSH009.SOURCE.ASM(SHOWREGS) on volume: SGLB14
My though is that the correct instruction should be:
BSM Rx_32,Ry_64
This is HLASM 6.0, PTF UK54260.
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
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