The PrOp does not talk about AMODEs. It talks about addressing modes. This
distinction is, however, a terminological not a substantive one. Bits 31 and
32 of the PSW are controlling, as in
PSW bits 31,32
| 0 | 0 | 24-bit addressing mode
| 0 | 1 | 31-bit addressing mode
| 1 | 1 | 64-bit addressing mode
These values control address generation during instruction execution. (The
topic is dealt with, lucidly, in Chapter 5, Program Execution, of the PrOp.)
About timings I have observed significant, measurable (by repetition)
differences between fullword and doubleword operations. I have not atttempted
to measure differences between, say, fullword and halfword operations. I
should expect to see the largest differences between doubleword and shorter
operands, but I do not know this. (Speaking very roughly now, the generic
problem is that when presented with too many bytes one must arrange to discard
some of them.)
Fetch width in general is a topic I don't know enough to recite on. It could
certainly be model-dependent, but I have no experience of a zArchitecture model
having a fetch less than 8 bytes in width. It is clear that fetch width must
be a multiple or submultiple of 8 bytes, but this truism which limits it to one
of 1, 2, 4, 8, 16, 32, 64, . . . bytes, is not very helpful; and in any case
cache operations complicate things greatly..
Perhaps one of our IBMers will be willing to be more specific about this.
Gilmore Ashland, MA 01721-1817 USA
