Fred,
it took me some time to actualy get what you do (not BASE64 - but the
RISBG) .... my guess it is the RISBG itself which is very slow and
apparently not very pipeline-freindly (and I have no idea about the
reasons).
How about using this
L R1,0(,R4) Load 4 source bytes
AHI R4,4(,R4) R4 past 4 source bytes
SLDL R0,6
SLL R1,2
SLDL R0,6
SLL R1,2
SLDL R0,6
SLL R1,2
SLDL R0,6
STCM R0,B'0111',0(R6) store 3 result bytes
AHI R6,3
I bet it is faster (and not only for the person looking at it).
Not that I am against new stuff. I actualy have been reverting to z10
instructions in code written for the public (from z11 instructions).
But there must be a gain for using them.
--
Martin
Pi_cap_CPU - all you ever need around MWLC/SCRT/CMT in z/VSE
more at http://www.picapcpu.de
