On Tue, 27 Dec 2011 16:08:43 -0600, McKown, John <[email protected]> wrote:
>What do you think of a hardware feature, selectable >via a bit in a control register, so that addresses >in "low core" can only be referenced via GPR0? That could be useful. >I.e. if you use any register as a base register in an >instruction, and that register contains F'0' (or D'0' >in AMODE 64) or x'80000000', then a program interrupt >occurs. That would also catch sloppy coding where an index register is specified rather than a base register. >Perhaps with some way in the binder to indicate that >the "interrupt if base register contents are NULL" >switch should be ON for a particular module. That could problematic. If I LOAD a module and call it with BASR, BASSM, etc., how would the code be invoked to set a control register bit? Remember that a load module can have more than one entry point. How would the bit be reset when the program returns? >I wonder if this would help with program bugs. Yes, it would. >It would definately stop the branch to location 0 when >a VCON is unsatisfied. The usual way to use a VCON is to load it into register 15 and issue a BR 15 instruction. In this case there is no base register. >And the interrupt would be on the branch instruction >instead of being in low memory. Breaking Event Address helps with this one. -- Tom Marchant
