Not well thought out, or at least not precisely expressed.
Consider the following code:
LA R0,0 put "low core" constant address of zero in R0
L R1,16(R0,R0) get the address of the CVT
* at this point, a program interrupt occurs.
Or perhaps the code can get into supervisor state first so that it can alter
the proper bit in Control Register 0 before attempting to fetch the address of
the CVT.
Neither way looks very useful.
Maybe I am missing something.
Bill Fairchild
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:[email protected]] On
Behalf Of McKown, John
Sent: Tuesday, December 27, 2011 4:09 PM
To: [email protected]
Subject: Idea for a possible enhancement to z architecture
I've been coding up a UNIX program in HLASM. One thing that I'm doing is "chain
chasing" using pointers. The end of chain is indicated by a pointer of binary
zeros: A(0). The code basically loops by doing an LT instruction of the next
pointer, followed by a JNZ. Works quite well. Now my mind is churning a bit. I
seen this type of thing in a lot of C code as well. But it depends on the
programmer remembering to check the next pointer for NULL. So what occurred to
me was: "Why doesn't the hardware do this?". That spawned an idea that I would
like your feedback on. What do you think of a hardware feature, selectable via
a bit in a control register, so that addresses in "low core" can only be
referenced via GPR0? When using GPR0 as either a base or index register, the
actual contents are actually and F'0' is used as the value. I don't know of any
exception to this rule. So why not extend it? I.e. if you use any register as a
base register in an instruction, and that register con!
tains F'0' (or D'0' in AMODE 64) or x'80000000', then a program interrupt
occurs. Granted, this could cause a "false positive" for those people who
reverse the meaning of the "base" and "index" registers. This could cause a
"false positive". Which is why it should be governed by a bit in a control
register. Perhaps with some way in the binder to indicate that the "interrupt
if base register contents are NULL" switch should be ON for a particular
module. I wonder if this would help with program bugs. It would definately stop
the branch to location 0 when a VCON is unsatisfied. And the interrupt would be
on the branch instruction instead of being in low memory.
Good idea? Or stupid?
John McKown
Systems Engineer IV
IT
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