At 17:40 +0000 on 12/28/2011, Bill Fairchild wrote about Re: Idea for
a possible enhancement to z architecture:
Not well thought out, or at least not precisely expressed.
Consider the following code:
LA R0,0 put "low core" constant address of zero in R0
L R1,16(R0,R0) get the address of the CVT
* at this point, a program interrupt occurs.
Or perhaps the code can get into supervisor state first so that it
can alter the proper bit in Control Register 0 before attempting to
fetch the address of the CVT.
Neither way looks very useful.
Maybe I am missing something.
It should never interrupt since when used as a Base or Index
register, the content of R0 is not referenced but treated as if it
contained 0. Now if you replaced R0 with any other register (such as
R2-R15) in the above code, then the trap can legitimately trigger.
Note that without the trap, the code would load the address of the
CVT into R1 no matter what registers were used as the BASE and INDEX
since the B+D+I = 16+0+0.
