This was due to my looking at the expansion of the CALL macro after using 
SYSSTATE ARCHLVL=2. The part of the expansion I was looking at was:

 BRAS 15,*+8
 DC V(epname)
 L 15,0(15,0)

And I immediately wondered by it was L 15,0(15,0) instead of how I am used to 
it: L 15,0(,15). Then it hit me. 0(15,0) is correct because it used 0 in the 
base register position, and by so doing was not really using a base, only an 
index. This caused the load instruction to load from the primary address space 
whereas 0(0,15) would have used the contents of AR15 when in AR mode, and might 
access the wrong address space. At least I am guessing that using a base 
register of 0 ends up effectively using an AR value of 0.

But that made me wonder why the z/Architecture does not specify that the 
contents of the AR register associated with the link register in any of the 
"branch and link" type instructions: BALR, BASR, BRAS, BRASL, and BASSM will be 
set to 0?

Anybody have any idea why these type of instructions don't set the AR?

Also, why the LAE instruction? Why doesn't the LA instruction act like the LAE 
instruction? If you're stepping through an address like: LA 1,1(,1) then AR1 
will be set to AR1, which is effectively doesn't change it. And if your in AR 
mode, what use is something like LA 1,OFFSET(0,10) do if AR1 is not equal to 
AR10? Some sort of "parallel address space" containing some sort of "copy" of 
the contents of the address space addressed by AR10? I.e. is the data accessed 
by the address OFFSET(0,10) but within a different address space likely to be 
of any use?

I'm so confused!

--
John McKown
Systems Engineer IV
IT

Administrative Services Group

HealthMarkets(r)

9151 Boulevard 26 * N. Richland Hills * TX 76010

(817) 255-3225 phone *

[email protected] * www.HealthMarkets.com



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