Sorry, but I meant BAL and BAS, not BALR or BASR. I often use these to set a 
pointer to an "in stream" data area or array. Like:

   BRAS R15,*+20
   DC   A(P0,P1,P2,P3)
   LM   R0,R3,0(R15)

That won't work, as is, in AR mode because I cannot be certain of the value in 
AR15. Of course, I could just prefix those instructions with

   LAE  R15,0(0,0)

I'm just trying to save an instruction. I guess IBM figured that forcing the 
user to use an LAE would take less CPU than setting the associated AR register 
for the link register for every BAL, BAS, BRAS, or BRASL executed. I don't 
really know how the CPU works internally. I.e. could it set the AR "in 
parallel" with other work in the branch instruction and so not increase the 
time required? And I don't know how complicated it would be to implement that 
in hardware.

I guess that's also why the LA was not "enhanced" to load the AR. It keeps the 
instruction simplier on the hardware level. Does anybody know if LA is "faster" 
than LAE?

And another crazy thought, why isn't there an instruction to load a register 
and its associated AR? Something like: LWA (Load With AR) and LWAG (grande). 
LAW[G][Y] r1,d1(i1,b1) where the address points to either 2 or 3 words. The Y 
is for "long displacement". The G is for 64 bit addresses. The storage area 
would a fullword AR value followed by a 1 or 2 word address. The access 
register seem strange in that there is only an STAM and LAM to load them in 
multiples from a offset+base (no index).

Oh, well, I wish there was a general document from IBM which explained why they 
chose the instructions that they chose. And perhaps why they chose to not 
implement some others.

--
John McKown
Systems Engineer IV
IT

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> -----Original Message-----
> From: IBM Mainframe Assembler List
> [mailto:[email protected]] On Behalf Of Edward Jaffe
> Sent: Tuesday, April 10, 2012 2:50 PM
> To: [email protected]
> Subject: Re: curiosity: In AR mode, why doesn't
> BALR/BASR/BRAS/BRASL set the value of the corresponding AR register ?
>
> On 4/10/2012 11:31 AM, McKown, John wrote:
> > But that made me wonder why the z/Architecture does not
> specify that the contents of the AR register associated with
> the link register in any of the "branch and link" type
> instructions: BALR, BASR, BRAS, BRASL, and BASSM will be set to 0?
> >
> > Anybody have any idea why these type of instructions don't
> set the AR?
>
> Unnecessary. Instruction fetch is always from the primary
> address space.
>
> --
> Edward E Jaffe
> Phoenix Software International, Inc
> 831 Parkview Drive North
> El Segundo, CA 90245
> 310-338-0400 x318
> [email protected]
> http://www.phoenixsoftware.com/
>
>

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