On 2017-07-30, at 22:57, Charles Mills wrote: > Nay. Many, many instructions are not atomic. On a single CPU, yes. For > multiple CPUs, not atomic. Until the z13 (?), for example, NI, OI and XI > were interruptible within a reference to a single byte. NI is actually > fetch, AND, store. It could be interrupted between the fetch and the store. > So two processors doing NI or OI on the same byte could get "logically > impossible" results. > Be careful with your use of "interrupt". To some readers it may mean a context switch by loading a new PSW, not what I believe you intend.
What was the performance cost of making NI, OI, and XI block-concurrent? I suspect many programs will never rely on this behavior, and have never used tne NIL and OIL macros, yet will bear the burden of any overhead. I understand that even in the S/360 the data path to memory was 16 bits or more, so MVI must also do a fetch, update, store. Why was there never a similar hazard when two processors MVI to different bytes of the same halfword? -- gil
