That's just PoOp-speak for "it works like you'd expect it to". Not that interesting.
sas On Fri, Sep 15, 2017 at 1:37 PM, Richard Kuebbing <[email protected]> wrote: > I find this intereesting: > > The second operand is fetched using the current > DAT and address-space controls in the PSW. > However, the branch address that is fetched from > the second-operand location is treated as an > instruction address and is treated as a real > address in the real mode, as a primary virtual > address in the primary-space mode, secondaryspace > mode, or access-register mode, and as a > home virtual address in the home-space mode. > > Not just an adcon but a "real address"! > > Richard > > -----Original Message----- > From: IBM Mainframe Assembler List [mailto:[email protected]] > On Behalf Of John McKown > Sent: Friday, September 15, 2017 12:47 PM > To: [email protected] > Subject: Re: interesting, to me, new z14 instruction: BIC > > On Fri, Sep 15, 2017 at 11:20 AM, Tony Harminc <[email protected]> wrote: > >> On 15 September 2017 at 11:46, Martin Truebner <[email protected]> >> wrote: >> > Did they forget BIRC (same as BIC, but the address of the storage is >> > relative to branch instruction). >> > >> > Yes, a table with routine-addresses will most of the time exist in >> > storage addressable with a base-register (or an Index-register)- but >> > what about the cases where this is not true? >> >> I don't think they forgot it; I think it's not useful for the scenario >> in question. That is, where the branch address is passed in storage >> (typically on a stack) from a calling routine. There are far fewer >> cases where the address of the branch address would be known at >> compile time and be instruction relative. Maybe you can suggest a >> realistic use case for this. > > >> What I found interesting is that there is only a 64-bit instruction >> (though it has no G in it); there is no 31-bit version. >> > > Well, I guess that IBM figured that saving 4 bytes in the "adcon" wasn't > worth the extra decoding. The current addressing mode determines whether the > branched to address is a 24, 31, or 64 bit address. As best as I can tell, > the excess bits are simply ignored. Like doing a fullword load into a > register in 24 bit mode to use as a branch address. The contents of the high > order byte are irrelevant and ignored. > > > >> >> Tony H. >> > > > > -- > UNIX was not designed to stop you from doing stupid things, because that > would also stop you from doing clever things. -- Doug Gwyn > > Maranatha! <>< > John McKown > > > ----------------------------------------- The information contained in this > communication (including any attachments hereto) is confidential and is > intended solely for the personal and confidential use of the individual or > entity to whom it is addressed. The information may also constitute a legally > privileged confidential communication. If the reader of this message is not > the intended recipient or an agent responsible for delivering it to the > intended recipient, you are hereby notified that you have received this > communication in error and that any review, dissemination, copying, or > unauthorized use of this information, or the taking of any action in reliance > on the contents of this information is strictly prohibited. If you have > received this communication in error, please notify us immediately by e-mail, > and delete the original message. Thank you -- sas
