On Mon, Aug 6, 2018 at 9:51 AM Paul Gilmartin < [email protected]> wrote:
> On 2018-08-06, at 08:35:57, Ed Jaffe wrote: > > > We use 'Jxx *+2' which disturbs no registers and is guaranteed to fail > with an 0C1. > > > I am *not* going to read the PoOps to learn why that "is guaranteed > to fail". I'm merely dismissing it as elitist opaque code. Comments > help only slightly. > Just in case anyone else is interested, given that Gil has disclaimed any interest at all. J *+2 generates the instruction: 7A44 0001 . The jump is actually to the x'0001' inside the J instruction, which is what "*+2" generates in HLASM -- two bytes beyond the instruction itself -- which is the PSW at the time of execution. The PoPS guarantees that opcode x'00' will never be implemented (old OS/360 PoPS did not have this guarantee). So, implicitly, J *+2 is guaranteed to generate a PIC 1 interrupt because of the target of the jump. This generates an S0C1 in z/OS. I don't know what it generates in other OSes (z/VSE, CMS, z/TPF, z/Linux). The only plus over an ABEND instruction, which I agree is best in most cases, is that there are fewer bytes and all the registers are in the RTM2WA work area. If anyone is still using SYSUDUMP or IPCS for processing dumps, as opposed to something like AbendAid. -- Between infinite and short there is a big difference. -- G.H. Gonnet Maranatha! <>< John McKown
