For the whole register, LGHI, LLILL (or HL, LH, or HH) are best. LLILF, LLIHF take up more space. XGR, SGR, SLGR set the CC.
For only the low half, XR, SR, SLR have the shortness advantage, and LHI the non-CC advantage. Chances are that the CC setting is irrelevant in timing on modern CPUs. The worst way to zero a register is more interesting. JCTG Rx,* is my favorite. If Rx is already 0, guess how long that will take. sas On Mon, Aug 10, 2020 at 8:24 PM Dan Greiner <[email protected]> wrote: > Several recent z Models include a feature that recognizes some > instructions that zero a register (or portion thereof) and bypass certain > pipeline stages for faster execution. I don't recall which models or which > instructions, but LHI, LGHI, SR, SGR, XR, and XGR seem to ring a bell. > > If this question is more than just an academic curiosity, then you will > have to seriously consider how frequently the register-clearing code will > be executed ... and will you EVER recoup the cycles spent re-assembling and > testing the updated code. > > As to LA and LAY, recall that the results of these instructions are > dependent on addressing mode, and they will not zero bits 0:31 of the > register in AMODE 24 or 31. > > The main consideration that I used in picking the which instruction to use > was code size — knocking myself silly trying to keep frequently-executed > code within the same page ... if not within the same cache line — so SR and > XR were preferred. A secondary consideration was whether I needed to > preserve a previously-set condition code — so LHI and LGHI were preferred. >
