On Tue, Nov 24, 2020 at 09:25:34AM -0800, Charles Mills wrote:
> The compilers now do a lot of using the high halves of registers as "scratch
> pads." So the upper half of the register might be storing some unrelated
> value.
>
> Charles
>
>
Even so - this could only be really meaningful in AMODE 31, if you want
to keep those unrelated values in the upper half of the register and
use the register to address the given item, then it could only be in
AMODE 31.
And, since it's AMODE 31, LARL doesn't touch the upper half of the 64-bit
register; from the POP for LOAD ADDRESS RELATIVE LONG:
In the 24-bit addressing mode, the address is placed in bit
positions 40-63, bits 32-39 are set to zeros, and bits 0-31 remain
unchanged. In the 31-bit addressing mode, the address is placed
in bit positions 33-63, bit 32 is set to zero, and bits 0-31
remain unchanged.
So, I think in this scenario you'd still be able to use LARL?
- Dave R -
p.s. The Dignus compilers will use the upper-halves of 64-bit registers
when the option to do so is enabled and the situation allows.
--
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Get your mainframe programming tools at http://www.dignus.com
