So yes, typically a branch table for return codes is going to be in the order of 6 (0,4,8,12,16,20) and anything else would be handled by the "you shouldn't be here" case. 95% of the time CIJE 15,0,RC0ROUTINE/CIJE 15,4,RC4ROUTINE/etc. would work just fine (I like that idea, especially when implemented as a macro). But, we do have cases with many branch targets, not as many as Tony's but still in the 10-20 range. In those cases. you are just as likely to have to traverse the entire list as the first entry making performance a possible issue.
This really stems out of a copy/paste error that I mentioned in the thread about ASMPUT. Someone copied a branch relative instruction from one subroutine to another and forgot to change the target address. In coming up with potential "solutions" (to avoid the issue in the future), one idea I had was to create label and branch macros that would enforce a "unique to this subroutine" rule. They worked fine but then I came across the branch table. I try to avoid using conditional assembly in open code so was working on a branch table structure that worked with the aforementioned label and branch macros. Thanks again for the input! *Mark* On Tue, Nov 23, 2021 at 12:34 PM Tony Thigpen <t...@vse2pdf.com> wrote: > I think Martin is really commenting that if you only have 3 branch > possibilities, then the overhead of the validation is greater than just > doing three Test-and-branch instruction pairs. > > I don't know about others, but I don't usually use a branch table unless > I have 8 or more values. Many of my branch tables have 100+ entries. > > Tony Thigpen > > Seymour J Metz wrote on 11/23/21 12:31 PM: > > ? > > > > What is a shorter way to do the error checking? > > > > > > -- > > Shmuel (Seymour J.) Metz > > http://mason.gmu.edu/~smetz3 > > > > ________________________________________ > > From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on > behalf of Martin Ward [mar...@gkc.org.uk] > > Sent: Tuesday, November 23, 2021 12:27 PM > > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > > Subject: Re: Base-less macros > > > > On 23/11/2021 17:12, Seymour J Metz wrote: > >> LTR R15,R15 > >> JM BADIX > >> CHI R15,LIMIT > >> JH BADIX > >> TML R15,3 > >> JNZ BADIX > >> J *+4(R15) > >> BRTAB EQU * > >> J RC0ROUTINE > >> J RC4ROUTINE > >> J RC8ROUTINE > >> LIMIT EQU *-BRTAB > > > > Three test and branch instruction pairs plus two unconditional > > branch instructions, all to avoid executing a sequence > > of up to three test and branch instruction pairs :-) > > > > -- > > Martin > > > > Dr Martin Ward | Email: mar...@gkc.org.uk | > http://secure-web.cisco.com/1Pzh0mz_8aE1yk4Zn65QdgWKxjXTYuplR0LTSWVThm5eBwv_XGYMaTUu-chekxBfi6Q9025E8Qko7Tv2AfAq4VKpPXZJATEnvK9yfCADRqS-MqJ-9CwXhQPcVAUaaVJisVYqePQcB1EgYhTEXUg6EMsRZGoSZYmbdXVC6DKXq6U8r16EOSntjBUqgbf2JkfOl98-JPqYFjgE8_O2ukkHD0bNk7EcYVFjZpL1RJqnISm5qT4Y1PLZTFqF7W4RLN3SouhBZKmQy9KILd6gufPlqfnEZ6XXLr886LHYJ7D4RI2pkwR_tUPju4DD8dBYH0dI5vbdm4BN1zPlh0lAnJdlARc5rcXUCQ658_9kIqdQ2ssUV8SW7IqhNvqBrN5QJARIDeNc6W-Q-LfKdo7Pk9GyTpPv0B3hR9SkveNdRnWPBZDBmkTzbbHhclfSRqf0xnmsZ/http%3A%2F%2Fwww.gkc.org.uk > > G.K.Chesterton site: > http://secure-web.cisco.com/1OoGY6MPQRndcjIvC1a1r8dwvjRs0IiXumRn9B23l7Qi4vovkS4Ad8DCdEzjy7ZIxLBepUzkEB_3bndzCEBbgp6ItZFwrsQSie-z0aU7oWtR4pD-YS5UwnfKWFfEM53hm7XEj8GMpX_xgRvBYE6TI0wql6IHyekYniK7_TXAPyRNm18FqTVb_EXc24xGkuM4ixs2eE2TlFlZFIZKuIvQCgjZs600JXzVB2Caqp-MsKzLomt4z2p5Y3oxjZF9k0tWw8BKgGSN-e2OHTuv1dZfxbT7sMdFq0_P0TneTPOkY5JnRjmQK04uRe9mgyNatqGClUiwzLK4C7cShMxI2X-pM21gz0CRfnAG77jKiBGCgCVy-6Qak1MF7G9FPhX9rdPIB8sOIEruuQuHWc0VVU9Ps4UvPqQIKmmIbtqJ76rIR9-r-TwsRyxErjP4aJaZlW7MQ/http%3A%2F%2Fwww.gkc.org.uk%2Fgkc > | Erdos number: 4 > > >
