All, to my knowledge, the FPRs got even numbers only because in the initial implementation they existed as register pairs(!) - hence the weird numbering scheme we still have today :-)
Kind regards, Abe Kornelis ============ Op 29/11/2021 om 15:22 schreef Seymour J Metz: > I'm not aware of any processor that FP registers beyond what IBM documented. > Certainly non of the functional specs manuals mentioned such a thing. > > >From my perspective it was a long way coming, but I'd bet that there are > >people here and on IBM-MAIN who never saw a processor with only 4. > > ________________________________________ > From: IBM Mainframe Assembler List <[email protected]> on > behalf of Peter Relson <[email protected]> > Sent: Monday, November 29, 2021 8:06 AM > To: [email protected] > Subject: Re: FPR usage question > > I wrote > <snip> > For z/OS, this question relates to each work unit and the question is > "does the work unit use FPRs 8-15 or VRs?". > If the answer is no, then that work unit does not save/restore those regs > upon undispatch/redispatch and thus saves some cycles. > </snip> > > "FPRs 8-15" is incomplete/inaccurate within that. It should be "FPRs > 1,3,5,7-15 or the floating point control register (FPCR)". > > Historically, only FPRs 0,2,4,6 existed and were saved/restored upon > undispatch/redispatch. Maybe Shmuel would know even the "pre-history" as > to whether FPRs 1,3,5,7 ever existed. > > The addition of the "additional floating point registers" (1,3,5,7-15 and > the FPCR) came with enablement by control register bit, with a program > interrupt upon usage without that control register bit (upon which program > interrupt, in many cases, the system would automatically activate > saving/restoring of the additional FPRs). > > Peter Relson > z/OS Core Technology Design
