The is a difference between what registers exist in the hardware and what is addressable by a S/360 (FSVO) program. Yes, there were processors where the microcode could address individual fileds within an FP register, but the instructions implemented in microcode could not do so until very late in the game, AFAIK. Certainly the first published reference that I have seen to 16 FP registers in the architecture was for the basic floating-point feature on S/370-ESA.
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 ________________________________________ From: IBM Mainframe Assembler List [[email protected]] on behalf of Robin Vowels [[email protected]] Sent: Monday, November 29, 2021 9:31 AM To: [email protected] Subject: Re: FPR usage question On 2021-11-30 00:06, Peter Relson wrote: > I wrote > <snip> > For z/OS, this question relates to each work unit and the question is > "does the work unit use FPRs 8-15 or VRs?". > If the answer is no, then that work unit does not save/restore those > regs > upon undispatch/redispatch and thus saves some cycles. > </snip> > > "FPRs 8-15" is incomplete/inaccurate within that. It should be "FPRs > 1,3,5,7-15 or the floating point control register (FPCR)". > > Historically, only FPRs 0,2,4,6 existed and were saved/restored upon > undispatch/redispatch. Maybe Shmuel would know even the "pre-history" > as > to whether FPRs 1,3,5,7 ever existed. My guess is that the register addresses 1, 3, 5, and 7 existed on S/360 internally, merely to enable the microcode to deal with double-precision FP arithmetic. > The addition of the "additional floating point registers" (1,3,5,7-15 > and > the FPCR) came with enablement by control register bit, with a program > interrupt upon usage without that control register bit (upon which > program > interrupt, in many cases, the system would automatically activate > saving/restoring of the additional FPRs).
