Peter R. may answer on his own, but my impression is that this VR/FPR overlap
is part of the hardware chip design of the FPU part of the z chips, and the
fact that the zarch SIMD VR instruction functionality was (probably) initially
aimed at mathematical computations that need FPU operations. Not sure that
could change in a future HW/chip design, but you never know.
Then again, they could adopt the mighty-mite box solution of using (a) separate
GPU('s) with MIMD operations embedded for this stuff. Look at what the
crypto-currency miners are doing with loads of GPU's slaved together.
Peter F.
-----Original Message-----
From: IBM Mainframe Assembler List <[email protected]> On Behalf
Of Phil Smith III
Sent: Wednesday, December 8, 2021 4:57 PM
To: [email protected]
Subject: Re: Vector register 23?
Peter Relson wrote, in part:
>the part about regs 8-15 bytes 0-7 is related to the fact that the VR
>storage overlaps the FPR storage.
Peter, I expect I'm not the only one who's amazed by this. Not that I know
enough to have a valid opinion, just that in this modren age of cheap memory
etc., it seems surprising that these would overlap. Do you know why this was
done? Is it something that could be "fixed" in a later machine, or is it now
baked into the ecosystem and thus basically how it's gonna be forever?
--
This message and any attachments are intended only for the use of the addressee
and may contain information that is privileged and confidential. If the reader
of the message is not the intended recipient or an authorized representative of
the intended recipient, you are hereby notified that any dissemination of this
communication is strictly prohibited. If you have received this communication
in error, please notify us immediately by e-mail and delete the message and any
attachments from your system.
