Back in late September, I posted a link to a series of PowerPoint slides that illustrate the operation of the z/Architecture vector-facility instructions. For those who missed it, you can find it on my Google Drive: https://drive.google.com/file/d/13OhBkhgbU7N6a20nVo5uEAnR-s3-Pyz8/view?usp=sharing
The Overview.ppt file clearly illustrates that bits 0-63 of vector registers 0-15 are one and the same as bits 0-63 of the corresponding floating-point registers. Since this has been baked into the hardware architecture since the z13's debut in 2015, I think that the chances of IBM changing it are slim (somewhere between zero and negative infinity). Considering that the vector floating-point instructions (Chapter 24) provide equivalent function to that of BFP instructions (Chapter 19), with additional operations, wider registers, and twice as many registers as BFP, it seems to be of little concern that the floating-point and vector registers overlap. I expect that an application that starts exploiting VR floating-point ops will find little use for the FP instructions.
