On Apr 19, 2022, at 16:59:54, Bernd Oppolzer <bernd.oppol...@t-online.de> wrote: > > The solution LPR ... LCR ... SRL looks OK for me. > LPR keeps a nonzero result, but with a positive sign, > What does this do for an operand of 0x80000000?
> LCR does the same, but enforces a negative sign, > So the sigh bit unconditionally 1. > and SRL moves the sign to the rightmost bit position. > Unconditionally 1 What am I miissing? > Am 19.04.2022 um 15:06 schrieb Ian Worthington: >> Noticed today that the GCC C compiler generated an unexpected sequence of >> instructions for an AND and TEST: >> >> **** bool overflow = (ccpm & carrybit) != 0; // check if carry bit set >> 109 .loc 1 189 0 >> 110 0078 5810B25C l %r1,604(%r11) # D.7949, ccpm >> 111 007c 5410B26C n %r1,620(%r11) # D.7949, carrybit >> 112 0080 1011 lpr %r1,%r1 # tmp54, D.7949 >> 113 0082 1311 lcr %r1,%r1 # tmp55, tmp54 >> 114 0084 8810001F srl %r1,31 # tmp56, >> 115 0088 4210B25B stc %r1,603(%r11) # tmp56, overflow -- gil
