What was the last model on which there was a timing difference among SLR, SR, XR? I don't remember one on S/370 or later.
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי ________________________________________ From: IBM Mainframe Assembler List <[email protected]> on behalf of Peter Relson <[email protected]> Sent: Thursday, November 16, 2023 10:07 AM To: [email protected] Subject: Re: ASMA057E Undefined operation code SR 15,15 Everyone came up with the right alternatives. Among XR, SLR, and SR, XR is thought best (not necessarily measurable better). If you don't need a condition code (and certainly if you need to preserve a condition code), LHI is thought best. I'm not sure to what extent the fact that the first three are 2-byte instructions and LHI is a 4-byte instruction comes into play. It is apparent that LHI creates a bigger instruction-space footprint. That in turn can lead to increased cache line usage. Peter Relson z/OS Core Technology Design
