An EX (EXRL) instruction does not alter the memory in which the cached
instruction is located, so it does not affect cache lines. However in
the case of the B vs NOP it could affect the predicted instruction path
pipeline and thus affect performance.
As a side note, with CICS V6, Instruction Execution Protection can be
enabled. It prevents instructions from being executed in memory which
was obtained with IEP specified. That includes any instruction which is
the object of an EX (EXRL) instruction.
On 2025-08-19 2:52 p.m., Steve Thompson wrote:
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I have been reading through this from the bottom and hadn't seen
any mention of the following:
At one shop I was in as a developer, we had a macro that would EX
an MVC so that it would be variable.
We had a macro that depended on execution time arithmetic to do x
MVCs and end with an EX of an MVC to take the place of an MVCL.
We found that it was faster to do 4 MVCs than an MVCL. So if the
length to be moved was greater than 1024 bytes, we did the MVCL,
otherwise....
OTOH, at the last shop I was in, B and NOP instructions were
modified by EX to make them NOP or B. And it seemed like this was
the STD way to handle logic for switching from processing one
type of record to another.
So here is the question for the hard core types: With z/Arch,
might this cause a processor stall because of a cache line of
code having been changed since that line was fetched? And how
much of a delay could this cause?
-- Regards,
Steve Thompson
Make Mainframes Great Again
They use far less Electricity than Clouds and can do more work
Gary Weinhold
Senior Application Architect
DATAKINETICS | Data Performance & Optimization
Phone:+1.613.523.5500 x216
Email: weinh...@dkl.com
Visit us online at www.DKL.com
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