It doesn't flush the cache line of the target instruction, but if the target is not already in the cache then it may preempt a cache line that will later have to be reloaded.
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר ________________________________________ From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> on behalf of Gary Weinhold <000017b1d53aa4ea-dmarc-requ...@listserv.uga.edu> Sent: Tuesday, August 19, 2025 3:15 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU <ASSEMBLER-LIST@LISTSERV.UGA.EDU> Subject: Re: Execute-Type Instructions External Message: Use Caution An EX (EXRL) instruction does not alter the memory in which the cached instruction is located, so it does not affect cache lines. However in the case of the B vs NOP it could affect the predicted instruction path pipeline and thus affect performance. As a side note, with CICS V6, Instruction Execution Protection can be enabled. It prevents instructions from being executed in memory which was obtained with IEP specified. That includes any instruction which is the object of an EX (EXRL) instruction. On 2025-08-19 2:52 p.m., Steve Thompson wrote: > EXTERNAL EMAIL ALERT This email originated from outside of > DataKinetics. Do not click links or open any attachments unless you > both recognize the sender, and know the content is safe. > > I have been reading through this from the bottom and hadn't seen > any mention of the following: > > At one shop I was in as a developer, we had a macro that would EX > an MVC so that it would be variable. > > We had a macro that depended on execution time arithmetic to do x > MVCs and end with an EX of an MVC to take the place of an MVCL. > We found that it was faster to do 4 MVCs than an MVCL. So if the > length to be moved was greater than 1024 bytes, we did the MVCL, > otherwise.... > > OTOH, at the last shop I was in, B and NOP instructions were > modified by EX to make them NOP or B. And it seemed like this was > the STD way to handle logic for switching from processing one > type of record to another. > > So here is the question for the hard core types: With z/Arch, > might this cause a processor stall because of a cache line of > code having been changed since that line was fetched? And how > much of a delay could this cause? > > -- Regards, > Steve Thompson > Make Mainframes Great Again > They use far less Electricity than Clouds and can do more work > > Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone:+1.613.523.5500 x216 Email: weinh...@dkl.com Visit us online at http://www.dkl.com/ E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system.
