On 27 March 2013 15:10, Peter Stuge <pe...@stuge.se> wrote: > Peter Stuge wrote: >> What *exactly* is meant by "PCI bus reset" here? > > So it's PCIe and not PCI. This is an important distinction. I should > have figured from the AR93xx.
same deal holds for PCIE. Read my other reply. > From Daniel's description above, it seems that the hardware has a > limitation in that it must not be reset more than once. That seems > like not so reliable PCIe IP, as long as the issue really is well > understood, but I'm not sure? > > I would really like to hear the exact details about what the hardware > requires. It handles multiple resets fine. It doesn't handle BIOS writers doing weird crap. Adrian _______________________________________________ ath9k-devel mailing list ath9k-devel@lists.ath9k.org https://lists.ath9k.org/mailman/listinfo/ath9k-devel
