???? 11/11/2013 3:15 PM, ?/? Kamran Nishat ??????:
Dear Alex,
Can you send me updates in driver to make it support 5/10Mhz channel
both at client and AP ath9k. Also how can i set my channel to 5/10Mhz
in settings.
Kamran
On Mon, Nov 11, 2013 at 2:16 PM, Alex Hacker <hac...@epn.ru
<mailto:hac...@epn.ru>> wrote:
Thank you Adrian. Yes I know, but I can not get it working with AR9390
(enterprise) chip too. :(
Alex.
_______________________________________________
ath9k-devel mailing list
ath9k-devel@lists.ath9k.org
https://lists.ath9k.org/mailman/listinfo/ath9k-devel
Dear all,
I am also trying to reduce channel width to 5/10 MHZ. So far I managed
to see the code inside the ath9k driver. More particulary in hw.c and
ar9003_phy.c the functions "IS_CHAN_QUARTER_RATE" and
"IS_CHAN_HALF_RATE" exist. These functions take values from the hw.h
file, #define IS_CHAN_HALF_RATE(c) (((_c)->channelFlags &
CHANNEL_QUARTER) !=0 . From what I understand, this function changes
the clockrate value which in turn affects the PLL value. In a paper
reported that these values are responsible for channel width.
The question is how can I enable these half/quarter rate functions. For
example when you want to set the channel width to 40MHZ, you simply
type: iw dev "XXX" set channel "X" HT40+ . Also is this possible for
AR9380 chipset and if so, is this possible via driver configuration? Is
there anyone of you who achieved this?
Best Regards
Tomas
_______________________________________________
ath9k-devel mailing list
ath9k-devel@lists.ath9k.org
https://lists.ath9k.org/mailman/listinfo/ath9k-devel
