void Wrote: > I'm not an expert, but the jittery data signal has to pass the 'master > clock gate' at the DAC. What comes out of the gate is jittery/noisy > again. > A flip-flop gate has a data input, a clock input, and a data output. Here's how it operates: any time the clock input switches from low to high, the data output is switched to match the level of the data input at that instant. The data output remains at that level until the next low-high clock transition. The time that the data arrives on the input pin does not affect the time that the output pin switches. The same clock signal is used to drive the clock input of every gate in the circuit, so the jitter between gates does not influence the timing of the signal at the final output -- only the jitter on the clock.
Basically, the only thing that affects the signal that you hear is the jitter in the clock at the DAC output. If the clock signal is generated right there, then jitter in earlier stages doesn't cause jitter at the output. The reason that with SPDIF, jitter in the transport induces jitter in the DAC, if because with SPDIF the clock is generated in the transport. If jitter at the data input of a circuit influences the timing of the output data, then something is corrupting the clock -- excessive impedance in the power and ground planes, bad signal routing, poor grounding scheme, etc. -- John Stimson _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
