>this thread was too big an invitation.< Interesting. So I guess some form of ring buffer to decouple the input word stream from the DAC wouldn't work as even a fractional difference in mean clock frequency between transport and DAC would lead to near instant buffer over/under runs.
So if a PLL is needed to lock the DAC clock to the input stream recovered clock, then that PLL circuit needs a super-stable reference clock itself and some form of damping to minimise tracking jitter. -- amcluesent ------------------------------------------------------------------------ amcluesent's Profile: http://forums.slimdevices.com/member.php?userid=10286 View this thread: http://forums.slimdevices.com/showthread.php?t=37044 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
