Sorry, I intended to reply to this, but got side tracked... NewBuyer;325130 Wrote: > If the digital datastream is mis-timed upon receipt due to sending-clock > and/or transmission-interface jitter, this mis-timed data will of course > be received as such at the next device, and merely be re-encoded by the > SRC. The data will be intact, but the timing of the data will not. So, > how can simply remapping mis-timed data into a higher sample-rate, > possibly "eliminate" any of the originally received jitter artifacts?
It works because the SRC doesn't need to rely on the received clock signal to know the timing. It knows that the incoming sample rate is 44.1k (or 48k or whatever), and it computes the new data based on that knowledge. Because it knows what the timing should be, it can ignore what it actually is, and force the data back on grid. As Patrick and I have discussed, this technique ONLY works to reduce/eliminate transmission-interface jitter. It does nothing to correct any jitter in the original Analog to Digital conversion, nor does it do anything to correct jitter at the Digital to Analog conversion. -- DCtoDaylight Audiophile wish list: Zero Distortion, Infinite Signal to Noise Ratio, and a Bandwidth from DC to Daylight ------------------------------------------------------------------------ DCtoDaylight's Profile: http://forums.slimdevices.com/member.php?userid=7284 View this thread: http://forums.slimdevices.com/showthread.php?t=50147 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
