DCtoDaylight;326085 Wrote: > Sorry, I intended to reply to this, but got side tracked... It works > because the SRC doesn't need to rely on the received clock signal to > know the timing. It knows that the incoming sample rate is 44.1k (or > 48k or whatever), and it computes the new data based on that knowledge. > Because it knows what the timing should be, it can ignore what it > actually is, and force the data back on grid. > > As Patrick and I have discussed, this technique ONLY works to > reduce/eliminate transmission-interface jitter. It does nothing to > correct any jitter in the original Analog to Digital conversion, nor > does it do anything to correct jitter at the Digital to Analog > conversion.
Thanks Dave for your patience and info. I have just recently studied the S/PDIF protocol a bit further, and I believe that I understand better now, what you are explaining. Thanks again! :) -- NewBuyer ------------------------------------------------------------------------ NewBuyer's Profile: http://forums.slimdevices.com/member.php?userid=7862 View this thread: http://forums.slimdevices.com/showthread.php?t=50147 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
