Matt, We have worked with that option for many projects already. Again, to get the program space needed for some of the projects we need to go with a surface mount chip such as the atmega128. Currently our chip of choice is the atmega1284p which gives us plenty of both flash and sram in a 40pin dip package. As for specific requirements, there are none yet. This whole idea is just that, an idea, that started percolating around in my head as I was reading through the python on a chip project today and I thought this would be a good place to get some hints on how feasible it might be and/or where to start digging to work on it myself.
Thanks, Ray On Sun, Mar 13, 2011 at 7:57 PM, <matt.vandewer...@csiro.au> wrote: > Is there a specific requirement for it to be a *serial* SRAM? You can easily > tie a 32k parallel SRAM to the external memory bus of many atmega devices > with just a bus latch ('373 or '573) and a single inverter. This xram is > trivially mappable to the heap and/or bss space using linker directives (or > linker scripts). > > Cheers, > -- > Matt van de Werken > Electronics Engineer > Mining Geoscience, CSIRO Earth Science and Resource Engineering > 1 Technology Ct Pullenvale QLD 4069 > P: 07 3327 4142 F: 07 3327 4455 M: 0400 538 608 > E: matt.vandewer...@csiro.au > "Those that do not understand UNIX are condemned to reinvent it, poorly" > - Henry Spencer _______________________________________________ AVR-GCC-list mailing list AVR-GCC-list@nongnu.org http://lists.nongnu.org/mailman/listinfo/avr-gcc-list